In data communication between devices, since the clock of the receiving device and that of the transmitting device are not synchronized with each other, and the clock frequencies are also not equal to each other due to differences in operation environments such as the power supply noise and the temperature, the receiving device needs to reproduce the clock based on the received data. This process is commonly referred to as “timing recovery” or “data clock recovery”.
A typical timing recovery technique repeats the process of generating a clock on the receiving side, detecting the phase difference between the clock and the received data, and adjusting the frequency or the phase of the clock based on the detected phase difference.
FIG. 23 shows a typical phase difference detection circuit. In this figure, 161 denotes a data detection circuit, 162 a clock detection circuit, and 163 a determination circuit. The data detection circuit 161 and the clock detection circuit 162 are flip flop circuits having data pins fixed to H level, clock pins receiving the received data and the clock, respectively, and reset pins receiving the reset signal output from the determination circuit 163. When the received data goes H, the output of the data detection circuit 161 goes H, which is output as an UP signal. Similarly, when the clock signal goes H, the output of the clock detection circuit 162 goes H, which is output as a DOWN signal. The determination circuit 163 monitors the output of the data detection circuit 161 and the output of the clock detection circuit 162, and outputs the reset signal when both are H. Thus, when the outputs of the data detection circuit 161 and the clock detection circuit 162 are both H, it is reset back to L. Therefore, the UP signal is output over a period of time equal to the phase difference when data comes before the clock signal, and the DOWN signal is output over a period of time equal to the phase difference otherwise. Thus, it is possible to detect how much the phase of the clock signal is ahead of or behind that of the data.
The phase difference detection using such a method can be realized with simple circuits, but it is difficult to use such a phase difference detection in high-speed data communication due to the output delay of flip flop circuits, etc. In order to solve such a problem, Patent Document 1 discloses a method in which the phase difference detection process is parallelized in high-speed data communication.
Patent Document 1 discloses a phase comparator in which the clock frequency of the receiving device is set to 1/(2N+1) (where N is an integer greater than or equal to 1) of the data rate f (f=1/T), and which uses 2N+1 phases of clock signals from the zeroth phase to the 2Nth phase with a phase difference of T therebetween to perform a parallel process using 2N+1 phase difference detection circuits so as to detect the phase difference between each clock signal and the data.
In the following description, K−1 (K is an integer greater than or equal to 0 and less than or equal to 2N) representing the phase number in a designation “K−1th-phase clock signal” is the remainder of division by 2N+1 when it is greater than or equal to 0 and is obtained as K+2N when it is a negative number.
FIG. 24 shows the phase comparator disclosed in Patent Document 1. In this figure, 140 denotes a phase difference detection circuit, 141 a comparison period detection circuit, 142 a window setting circuit, 143 a transition point detection circuit, 144 a reference point detection circuit, 145 a determination circuit, and 146 a delay circuit. The phase comparator includes 2N+1 each of the phase difference detection circuits 140, the comparison period detection circuits 141 and the window setting circuits 142.
The Kth comparison period detection circuit 141, i.e., the Kth(K is an integer from 0 to 2N) one of the 2N+1 comparison period detection circuits, examines the Kth-phase clock signal and the (K−1)th-phase clock signal so as to output a signal indicating a period for comparing the phase of the Kth-phase clock signal with that of the data when the K-phase clock signal is L and the (K−1)th-phase clock signal is H. The Kth window setting circuit 142 takes in the output signal of the Kth comparison period detection circuit 141 at the rising edge of the data, and holds it until the (K+1)th-phase clock signal goes H. This is output as the Kth comparison enable signal.
In the phase difference detection circuit 140, the transition point detection circuit 143 outputs the UP signal in synchronism with the rising edge of the data, and the reference point detection circuit 144 outputs the DOWN signal in synchronism with the rising edge of the clock signal. The determination circuit 145 outputs a clear signal that resets both of the outputs of the transition point detection circuit 143 and the reference point detection circuit 144 when the UP signal and the DOWN signal are both H or when the comparison enable signal is L. As a result, the phase difference detection circuit 140 outputs nothing while the comparison enable signal is L, and operates similar to the phase difference detection circuit described above with reference to FIG. 23 when the comparison enable signal goes H.
The Kth phase difference detection circuit 140 receives the Kth comparison enable signal, data that is delayed by 0.5 T by the delay circuit 146 as the data, and the Kth-phase clock signal as the clock signal, thereby detecting the phase difference between the 0.5 T-delayed data and the Kth-phase clock signal and outputting the UP signal or the DOWN signal based on the result only while the Kth enable signal is H.
FIG. 25 shows a timing diagram of the phase comparator of Patent Document 1. For the sake of simplicity, only the operation of the first phase difference detection circuit will be described, wherein the period of the clock is assumed to be ⅕ of the data rate.
In this figure, 1501 to 1505 denote zeroth- to fourth-phase clock signals, respectively, 1506 an output signal of the first comparison period detection circuit 141, 1507 a first comparison enable signal, 1508 data, 1509 0.5 T-delayed data, 1510 and 1511 an UP signal and a DOWN signal, respectively, and 1512 a clear signal.
The first comparison period detection circuit 141 outputs the signal 1506 which is L only during a period between the rising edge of the zeroth-phase clock signal 1501 and that of the first-phase clock signal 1502. The first comparison enable signal 1507, which is the output of the first window setting circuit, latches the signal 1506 in synchronism with the rising edge of the data 1508 to output a reverse signal thereof, and is reset when the second clock signal 1503 goes H. Thus, the first comparison enable signal is H if there is a rising edge of the data during a period in which the zeroth-phase clock signal 1501 is H and the first-phase clock signal 1502 is L, and remains L otherwise.
During a period in which the first comparison enable signal 1507 is L, the clear signal 1512 of the first phase difference detection circuit 140 is L, thus resetting the transition point detection circuit 143 and the reference point detection circuit 144. When the first comparison enable signal 1507 goes H, the clear signal 1512 also goes H, thus starting the phase comparison operation. The reference point detection circuit 144 outputs the DOWN signal 1511 in synchronism with the rising edge of the first-phase clock signal 1502, and the transition point detection circuit 143 outputs the UP signal 1510 in synchronism with the rising edge of the 0.5 T-delayed data 1509. Since the figure shows a case where the 0.5 T-delayed data 1509 is lagged behind the first-phase clock signal 1502, the clear signal 1512 output from the determination circuit 145 goes L at a point in time when the UP signal 1510 is output, thus resetting the UP signal 1510 and the DOWN signal 1511 to L. Then, as the UP signal 1510 and the DOWN signal 1511 go L, the clear signal 1512 goes back H.
Thus, data transitions occurring during a period between the rising edge of the zeroth-phase clock signal 1501 and that of the first-phase clock signal 1502 are processed by the first phase difference detection circuit 140 as described above. Data transitions occurring in other periods are similarly processed by corresponding phase difference detection circuits, thus performing a parallel phase comparison process.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2004-15689